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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF40192B MSI 4-bit up/down decade counter
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
4-bit up/down decade counter
DESCRIPTION The HEF40192B is a 4-bit synchronous up/down decade counter. The counter has a count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel load input (PL), four parallel data inputs (P0 to P3), an asynchronous master reset input (MR), four counter outputs (O0 to O3), an active LOW terminal count-up (carry) output (TCU) and an active LOW terminal count-down (borrow) output (TCD). The counter outputs change state on the LOW to HIGH transition of either clock input. However, for correct
HEF40192B MSI
counting, both clock inputs cannot be LOW simultaneously. The outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum count state of `9', the next HIGH to LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on P0 to P3 is asynchronously loaded into the counter. A HIGH on MR resets the counter independent of all other input conditions. The counter stages are of a static toggle type flip-flop.
Fig.2 Pinning diagram.
HEF40192BP(N): 16-lead DIL; plastic (SOT38-1) Fig.1 Functional diagram. HEF40192BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF40192BT(D): 16-lead SO; plastic PINNING PL P0 to P3 CPU CPD MR TCU TCD O0 to O3 parallel load input (active LOW) parallel data inputs count-up clock pulse input (LOW to HIGH, edge-triggered) count-down clock pulse input (LOW to HIGH, edge-triggered) master reset input (asynchronous) buffered terminal count-up (carry) output (active LOW) buffered terminal count-down (borrow) output (active LOW) buffered counter outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications (SOT109-1) ( ): Package Designator North America
January 1995
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Philips Semiconductors
Product specification
4-bit up/down decade counter
HEF40192B MSI
Fig.3 Logic diagram (continued on next page).
January 1995
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Philips Semiconductors
Product specification
4-bit up/down decade counter
HEF40192B MSI
Fig.4 Logic diagram (continued from Fig.3).
January 1995
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Philips Semiconductors
Product specification
4-bit up/down decade counter
FUNCTION TABLE MR H L L L PL X L H H H CPU X X CPD X X H MODE reset (asyn.) parallel load count-up count-down Notes
HEF40192B MSI
1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition
Logic equations for terminal count: TC D = O 0 O 1 O 2 O 3 CP D TC U = O 0 O 3 CP U
Fig.5 State diagram.
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 550 fi + (foCL) x VDD2 2400 fi + (foCL) x VDD2 6500 fi + (foCL) x VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
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Philips Semiconductors
Product specification
4-bit up/down decade counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CPU On HIGH to LOW 5 10 15 5 LOW to HIGH CPD On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CPU TCU HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CPD TCD HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW MR TCU LOW to HIGH MR TCD HIGH to LOW PL On HIGH to LOW 10 15 5 10 15 5 10 15 5 10 15 5 10 15 tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 210 85 60 170 70 50 210 85 65 170 70 50 125 50 35 95 40 30 140 55 40 100 40 30 195 80 60 145 60 45 365 130 100 185 75 55 415 165 120 340 140 100 420 170 125 340 140 100 250 100 70 185 80 60 280 110 80 195 85 65 390 160 120 285 115 90 730 265 205 360 150 110 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX.
HEF40192B MSI
TYPICAL EXTRAPOLATION FORMULA 183 ns + (0,55 ns/pF) CL 74 ns + (0,23 ns/pF) CL 52 ns + (0,16 ns/pF) CL 143 ns + (0,55 ns/pF) CL 59 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 183 ns + (0,55 ns/pF) CL 74 ns + (0,23 ns/pF) CL 57 ns + (0,16 ns/pF) CL 143 ns + (0,55 ns/pF) CL 59 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 98 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 113 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 168 ns + (0,55 ns/pF) CL 69 ns + (0,23 ns/pF) CL 52 ns + (0,16 ns/pF) CL 118 ns + (0,55 ns/pF) CL 49 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 338 ns + (0,55 ns/pF) CL 119 ns + (0,23 ns/pF) CL 92 ns + (0,16 ns/pF) CL 158 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 47 ns + (0,16 ns/pF) CL
January 1995
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Philips Semiconductors
Product specification
4-bit up/down decade counter
HEF40192B MSI
TYP. 145 MAX. 290 120 90 ns ns ns TYPICAL EXTRAPOLATION FORMULA 118 ns + (0,55 ns/pF) CL 49 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL
VDD V 5 LOW to HIGH 10 15
SYMBOL MIN.
tPLH
60 45
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH Set-up time Pn PL Hold time Pn PL Minimum CPU or CPD pulse width; LOW Minimum MR pulse width; HIGH Minimum PL pulse width; LOW Recovery time for MR Recovery time for PL Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRPL tRMR tWPLL tWMRH tWCPL thold tsu 160 60 50 10 5 5 150 50 35 180 70 60 120 45 30 125 70 50 90 35 25 2,5 7 9 tTLH tTHL SYMBOL MIN. TYP. 60 30 20 60 30 20 80 30 25 -70 -25 -20 75 25 20 90 35 30 60 20 15 65 35 25 45 15 10 5 14 18 MAX. 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz see also waveforms Fig.6 TYPICAL EXTRAPOLATION FORMULA 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
January 1995
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Philips Semiconductors
Product specification
4-bit up/down decade counter
HEF40192B MSI
Fig.6
Waveforms showing recovery times for PL and MR, minimum pulse widths for CPU, CPD, PL and MR, and set-up and hold times for P to PL. Set-up times and hold times are shown as positive values but may be specified as negative values.
January 1995
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Philips Semiconductors
Product specification
4-bit up/down decade counter
HEF40192B MSI
Fig.7 Timing diagram.
APPLICATION INFORMATION Some examples of applications for the HEF40192B are: * Up/down difference counting * Multistage ripple counting * Multistage synchronous counting.
Fig.8 Example of cascaded HEF40192B ICs.
January 1995
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